3+ hour, 17+ min ago  (623+ words) As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching transistors is becoming increasingly difficult to dissipate. Engineers are turning to finite element modeling with adaptive meshing to accurately simulate thermal conduction profiles....

3+ hour, 18+ min ago  (330+ words) Critical aspects of ensuring robust security and efficient software development for AI chips. The post Building an AI Chip: Security, Software Development, and Lifecycle Management appeared first on Semiconductor Engineering. The third white paper in our series, "Building an AI…...

2+ hour, 47+ min ago  (271+ words) MBSE for multiphysics; traceability vs. tracking; UALink VIP; EM simulation; code migration; SOI. Synopsys" Jayraj Nair checks out how a model-based systems engineering workflow can help manage the complex multiphysics analysis needed to optimize heterogeneous systems. Cadence"s Jamdagni Trivedi…...

2+ day, 3+ hour ago  (1157+ words) High-speed data movement will be required in future vehicles, probably including optical, but challenges persist. The massive amount of data moving through a modern vehicle has far outstripped the capabilities of the traditional CAN bus. In its place, Automotive Ethernet…...

4+ day, 14+ hour ago  (734+ words) A new technical paper, "Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems," was published by the University of Texas, Austin, Intel Labs, Symmetry Systems, Microsoft and Georgia Tech. Abstract "Rapid progress in generative AI has…...

4+ day, 15+ hour ago  (703+ words) A new technical paper, "Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors," was published by researchers at Pohang University of Science and Technology. Abstract "Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its…...

6+ day, 3+ hour ago  (552+ words) Closing the gap between warpage simulation results and actual measurement data. Fig. 1: Overview of the quarter symmetric, 2 block, CA95 strip geometry without epoxy molding compound (EMC). The baseline geometry used in the simulations was a 2 block CA95 (240 x 95 mm) strip. The unit was…...

6+ day, 3+ hour ago  (482+ words) Matching a simulated device to its real-world counterpart with sub-nanometer accuracy. In modern semiconductor process integration, rapid and well-informed path finding is essential for on-time product release. Virtual Design of Engineering (DOE) and predictive modeling can expose integration risks early;…...

6+ day, 3+ hour ago  (445+ words) Co-packaged optics face scaling challenges such as bandwidth density mismatches, assembly complexity, and the need for precise fiber alignment. The rapid evolution of Artificial Intelligence (AI) has surpassed the capabilities of traditional monolithic compute architectures. The industry is shifting toward…...

6+ day, 3+ hour ago  (930+ words) High'NA EUV's reduced field size is driving new innovation in optical proximity correction and mask synthesis. The post Exploring The Frontiers Of Lithography And Patterning: Highlights From SPIE Advanced Lithography + Patterning 2026 appeared first on Semiconductor Engineering. Exploring The Frontiers Of…...